This application claims priority to Italian Patent Application Serial No. RM2000A000698 filed Dec. 28, 2000, which is commonly assigned.
The present invention relates generally to semiconductor memory devices, and in particular, the present invention relates to supply noise reduction for controlling column selection in a semiconductor memory device.
Semiconductor memory devices are rapidly-accessible memory devices. In a semiconductor memory device, the time required for storing and retrieving information generally is independent of the physical location of the information within the memory device. Semiconductor memory devices typically store information in a large array of cells. A group of cells are electrically connected together by a bit line, or data line. An electrical signal is used to program a cell or cells.
Computer, communication and industrial applications are driving the demand for memory devices in a variety of electronic systems. One important form of semiconductor memory device includes a non-volatile memory made up of floating-gate memory cells called flash memory. Computer applications use flash memory to store BIOS firmware. Peripheral devices such as printers store fonts and forms on flash memory. Digital cellular and wireless applications consume large quantities of flash memory and are continually pushing for lower voltages and higher densities. Portable applications such as digital cameras, audio recorders, personal digital assistants (PDAs) and test equipment also use flash memory as a medium to store data.
As operating voltages continue to decrease, operation of the memory device must come under tighter constraints. Lower operating voltages lead to lower operating margins. In turn, lower operating margins increase the demands on sensing circuits and related circuits for accessing a memory cell and sensing the data contained therein. For example, sensing devices often rely on a voltage differential to determine the programmed state of a memory cell, either a voltage differential between a target bit line and a reference voltage or a voltage differential between a target bit line and a threshold voltage. As operating voltages are reduced, such sensing devices often must be capable of distinguishing between smaller differentials.
Semiconductor memory devices generally contain a vast number of memory cells arranged in rows and columns. To access a target memory cell, one or more levels of decoding are used. As an example, a memory device may have millions of memory cells, but may only have 128 sensing devices, i.e., devices capable of detecting a programmed state of the memory cell and thus its data value. A decoding scheme is necessary to couple one of the millions of memory cells, i.e., the target memory cell, to one of the sensing devices as each sensing device may be selectively coupled to hundreds of thousands of individual memory cells.
A common decoding scheme may include a number of memory cells coupled to a local bit line, a number of local bit lines selectively coupled to a global bit line, and a number of global bit lines selectively coupled to a sensing device. A first pass circuit couples one of the local bit lines to its associated global bit line in response to a first control signal. A second pass circuit couples one of the global bit lines to its associated sensing device in response to a second control signal. A control signal to the target memory cell""s word line actively couples that memory cell to its associated local bit line, thus allowing the sensing device to detect its programmed state. The pass circuits risk the introduction of undesirable signal noise in the sensing operation. Reduced sensing margins lead to reduced tolerance of signal noise, i.e., signal noise is more likely to lead to an erroneous data value indication.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternate circuits and methods for accessing a memory cell for sensing in a memory device adapted for low-voltage operation.
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
Column select circuits are described for improved immunity to supply potential noise during sensing of the programmed state of a target memory cell. Such column select circuits are especially beneficial to low-voltage memory devices, such as those operating at supply potentials of 1.6-2.2V or below. Such column select circuits contain driver circuits having a filtered path and an unfiltered path for applying a supply potential to a gate of a pass transistor. The unfiltered path is utilized during a first sensing phase, such as during decoding or precharging of the bit lines, when transition speed of the pass transistors is desired. The filtered path is utilized at least during a second sensing phase while the sensing device is detecting the programmed state of the target memory cell. By reducing the noise of the supply potential using the filtered path, margins are improved on the sensing device and the sensing device is thus capable of operating at lower supply potentials with increase reliability.
For one embodiment, the invention provides a column select circuit having a pass transistor and further having a driver circuit coupled to supply a gate bias to a gate of the pass transistor. The driver circuit includes an output coupled to the gate of the pass transistor, a filtered path and an unfiltered path. The unfiltered path has a first potential node coupled to receive a first supply potential, and a first field-effect transistor interposed between the first potential node and the output. The filtered path has a second potential node coupled to receive a second supply potential, and a second field-effect transistor interposed between the second potential node and the output. The driver circuit has a first state to couple the gate of the pass transistor to the second potential node through the filtered path and to isolate the gate of the pass transistor from the first potential node. The driver has a second state to couple the gate of the pass transistor to at least the first potential node through the unfiltered path. The driver has a third state to isolate the gate of the pass transistor from both the first potential node and the second potential node.
The filtered path may include an RC filter interposed between the second potential node and the second field-effect transistor to reduce noise from the supply potential received at the second potential node. The driver circuit may further include a third field-effect transistor interposed between the gate of the pass transistor and a third potential node, wherein the third potential node is coupled to receive a third potential such as a ground potential. The gate of the pass transistor may be coupled to the third potential node when the column select circuit is in the third state.
For a further embodiment, the driver circuit is responsive to a first control signal and a second control signal such that the first field-effect transistor is activated when the first control signal has a first logic level and the second control signal has a first logic level, the first field-effect transistor is deactivated and the second field-effect transistor is activated when the first control signal has a second logic level and the second control signal has its first logic level, and the first field-effect transistor and the second field-effect transistor are deactivated when the second control signal has a second logic level regardless of a logic level of the first control signal. For a still further embodiment, the second field-effect transistor is also activated when the first control signal has its first logic level and the second control signal has its first logic level. The first logic level of the first control signal and the first logic level of the second control signal may be the same logic level. Similarly, the second logic level of the first control signal and the second logic level of the second control signal may be the same logic level.
For another embodiment, the invention provides a method of operating a memory device. The method includes deactivating a pass transistor during a non-sensing phase to isolate a target memory cell from a sensing device, and activating the pass transistor during first and second sensing phases to permit coupling of the target memory cell to the sensing device. Activating the pass transistor during the first sensing phase includes coupling a gate of the pass transistor to a first potential node while activating the pass transistor during the second sensing phase includes coupling the gate of the pass transistor to a second potential node through a filtered path and isolating the gate of the pass transistor from the first potential node. The method further includes sensing a programmed state of the target memory cell during the second sensing phase, while the gate of the pass transistor is coupled to the second potential node through the filtered path and while the gate of the pass transistor is isolated from the first potential node. For a further embodiment, activating the pass transistor during the first sensing phase further includes coupling the gate of the pass transistor to the second potential node through the filtered path.
For yet another embodiment, the method of operating a memory device further includes applying a first control signal to a first input of a NAND gate, applying a second control signal to a second input of the NAND gate, and applying the second control signal to an input of an inverter. The output of the NAND gate is applied to a gate of a first p-channel field-effect transistor coupled between the first potential node and the gate of the pass transistor while the output of the inverter is applied to a gate of a second p-channel field-effect transistor coupled between the second potential node and the gate of the pass transistor. The second control signal has a logic high level during the first and second sensing phases, such that the output of the inverter activates the second p-channel field-effect transistor during the first and second sensing phases. The first control signal has a logic high level during the first sensing phase, such that the output of the NAND gate activates the first p-channel field-effect transistor during the first sensing phase. The first control signal has logic low level during the second sensing phase, such that the output of the NAND gate deactivates the first p-channel field-effect transistor during the second sensing phase.
For further embodiments, the invention provides memory devices and electronic systems containing column select circuits of the type described herein. The invention further provides methods and apparatus of varying scope.